The present invention relates to a semiconductor integrated circuit device (hereinafter simply referred to as semiconductor device) for use in, for example, a liquid crystal driver or the like, and more particularly, relates to an electrode pad structure of a semiconductor device.
Conventionally, semiconductor chips (semiconductor devices) featuring a double metal structure have been mass-produced, and most of the semiconductor chips of this type are arranged so that each includes an electrode pad 70 in an area other than a circuit element area therein, as shown in FIG. 19.
More specifically, for example, a silicon oxide film (hereinafter referred to as CVD-silicon oxide film) 55 formed by the low-pressure chemical vapor deposition (CVD) method and a boron phospho-silicate glass (BPSG) film 56 are laminated on a silicon substrate 51 in this order. On the BPSG film 56, a barrier metal layer 58 and a first metal layer 59 are provided in this order as wiring materials.
The first metal layer 59 is made of aluminum or aluminum alloy containing silicon or copper siliside. However, in the case where aluminum or aluminum-alloy wires are solely provided, the liability of the device is impaired by halation occurring in a photo resist process, stress migration due to thermal stress, or the like. Therefore, in the case where it is formed to a thickness of 1 xcexcm or less, the first metal layer 59 is deposited on the barrier metal layer 58 made of a refractory metal such as titanium, tungsten, or titanium-tungsten, or silicide of such refractory metal, or a refractory metal oxinitride.
On the first metal layer 59, an interlayer insulating film 60 which is generally composed of a first interlayer insulating film 60a, a second interlayer insulating film 60b, a third interlayer insulating film 60c. The first interlayer insulating film 60a and the third interlayer insulating film 60c are films made of a silicon compound, such as silicon oxide films or silicon nitride films. The second interlayer insulating film 60b is formed by the spin-on-glass (SOG) method with which unevenness caused as a result of depositing the first metal layer 59 are eliminated, so that a flat surface is obtained.
A second metal layer 64 is provided on the first metal layer 59 with a barrier metal layer 63 therebetween, in a through hole formed in the interlayer insulating film 60. In other words, in the through hole, the interlayer insulating film 60 for insulation does not exist between the first metal layer 59 and the second metal layer 64.
On the interlayer insulating film 60 and the second metal layer 64, there is provided a passivation film 65 (65a and 65b) made of phospho-silicate glass (PSG) or silicon nitride. According to the bonding method such as the inner lead bonding (ILB) method, as shown in FIG. 19, a barrier metal layer 66 made of a refractory metal such as titanium-tungsten is formed on the passivation film 65 (65a and 65b) and on the second metal layer 64, and further, a gold bump 67 is formed on the barrier metal layer 66.
Incidentally, a semiconductor chip which is formed by providing an electrode pad 70 on an active element 50 of an electric circuit as shown in FIG. 20, i.e., by xe2x80x9cthe area pad techniquexe2x80x9d, is recently mass-produced. By this technique whereby the electrode pad 70 is formed on the active element 50, a portion below the pad which has not been utilized is now effectively utilized, thereby allowing reduction of the size of the chip. Besides, the electrode pad 70 is provided in any area of the chip, whereby the freedom degree relating to the design of the semiconductor chip is raised. The following description will explain the wafer manufacturing process of the semiconductor chip of this type, while referring to FIGS. 20 and 21(a) through 21(d).
First, as shown in FIG. 21(a), a silicon oxide film 52 is formed on a silicon substrate 51, and a polysilicon film 53 as a conductive layer is formed on the silicon oxide film 52, so that the polysilicon film 53 constitutes a gate electrode. Then, as shown in FIG. 21(b), diffusion layers 54a and 54b are formed in the silicon substrate 51, and thereafter, a CVD-silicon oxide film 55 is formed by the low-pressure CVD method.
Subsequently, as shown in FIG. 21(c), a BPSG film 56 is formed at a normal pressure on the CVD-silicon oxide film 55, and then, the CVD-silicon oxide film 55 and the PBSG film 56 are photo-etched, so that contact holes 57a and 57b are formed. Thereafter, by the sputtering method, barrier metal layers 58a and 58b made of titanuim-tungsten or the like, first metal layers 59a and 59b for metal wiring, which are made of aluminum or aluminum alloy such as aluminum-silicon, aluminum-coppersilicon, or the like. Then, dry-etching is conducted with respect to the barrier metal layers 58a and 58b, and the first metal layers 59a and 59b, to obtain wires desirably arranged.
Next, as shown in FIG. 21(d), (1) a first interlayer insulating layer 60a composed of a silicon oxide film, a silicon nitride film, or the like, (2) a second interlayer insulating film 60b composed of a film formed by the SOG method (hereinafter referred to as an SOG film) or the like, and (3) a third interlayer insulating film 60c composed of a silicon oxide film, a silicon nitride film, or the like, are laminated in this order on the PBSG film 56 and the first metal layer 59a and 59b, so that an interlayer insulating film 60 having a trilaminar structure is formed.
The reason why the second interlayer insulating film 60b is provided between the first interlayer insulating film 60a and the third interlayer insulating film 60c, whereby these three layers constitutes the interlayer insulating film 60, is that gas such as steam from, for example, the SOG film as the second interlayer insulating film 60b, upon heat application thereto in the manufacturing process, would be prevented from intruding into the upper and lower layers. In the case where the silicon oxide films or the silicon nitride films are not provided so as to sandwich the SOG film, the gas may cause leakage (this phenomenon is hereinafter referred to as leakage defect).
Note that, to block the gas generated from the SOG film, the silicon nitride film which has a gas blocking property superior to that of the silicon oxide film is preferably used. However, if the SOG film is provided between the silicon nitride films, the interlayer insulating film 60 might be swollen due to gas pressure in some cases, and in the worst case, the interlayer insulating film 60 cannot be formed.
Subsequently, after forming a through hole in the interlayer insulating film 60 as shown in FIG. 20, a barrier metal layer 63 made of titanium-tungsten and a second metal layer 64 made of aluminum or an aluminum alloy are formed thereon as a pad metal and a wire, respectively.
Thereafter, the passivation film 65 (65a and 65b) made of PSG or silicon nitride is formed at a predetermined position on the second metal layer 64 in a manner such that the passivation film 65 may not be damaged upon bonding. Here, as shown in a plan view of in FIG. 22, an opening is formed in the passivation film 65 (65a and 65b) so that an edge 65c of the opening (hereinafter referred to as an opening edge 65c) is positioned at a distance of 2.5 xcexcm to 10xcexcm toward inside from an edge 64a of the second metal layer 64. In the case where gold wires or aluminum alloy wires are bonded to the second metal layer 64 as the pad metal by the wire bonding method, the process ends with this step, and the semiconductor chip wafer is completed.
On the other hand, in the case where the ILB method is used as the bonding method, a barrier metal layer 66 made of a refractory metal such as titanium or titanium-tungsten is deposited on the second metal layer 64 and the passivation film 65 (65a and 65b) by the sputtering method, and thereafter, the gold bump 67 is formed by the electric plating method. Then, an inner lead 68 (see FIG. 23) is bonded to the gold bump 67.
However, in the case of a semiconductor chip of the conventional area pad structure, if the wire bonding or the inner lead bonding is conducted under excessive conditions or if an external force is applied thereto after the bonding, a portion under the electrode pad 70 may be damaged and broken as shown in FIG. 23, and the barrier metal layer 63 may peel off the third interlayer insulating film 60c. As a result, the electrode 70 comes off (open defect), whereby a serious problem in quality such as the breaking of a wire (wire breaking defect) occurs.
The causes of this problem are: (1) the second interlayer insulating film 60b composed of a mechanically fragile thing such as an SOG film exists under the electrode pad 70; and (2) the third interlayer insulating film 60c made of PSG or BPSG, and the barrier metal layer 63 made of a refractory metal such as titanium-tungsten do not have adherence to each other.
Thus, in the conventional semiconductor chip arrangement, drawbacks such as breakdown of the portion under the pad upon bonding or exfoliation of the pad cannot be sufficiently prevented. Therefore, a semiconductor device having a structure such that occurrence of such drawbacks is prevented is now demanded.
The object of the present invention is to provide a semiconductor device of an area pad structure with which breakdown of a part under a pad and exfoliation of the pad can be avoided.
A semiconductor device of the present invention is characterized in comprising (1) an active element provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a pad metal for an electrode pad, the pad metal being provided on the interlayer insulating film, (4) a barrier metal layer provided on the active element with the interlayer insulating film therebetween, so that the pad metal is provided on the barrier metal layer, and (5) an insulating film having high adherence to the barrier metal layer, the insulating film being provided between the interlayer insulating film and the barrier metal layer.
According to the above arrangement, to form a semiconductor device by providing an interlayer insulating film and a barrier metal layer on an active element on a semiconductor substrate, an insulating film having high adherence to the barrier metal layer is provided between the barrier metal layer and the interlayer insulating film. Therefore, the adherence between the barrier metal layer, the insulating film, and the interlayer insulating film is surely enhanced. As a result, in the case, for example, an external force is applied to the electrode pad upon bonding with respect to the same, the barrier metal layer does not come off the part thereunder.
Therefore, with the aforementioned arrangement, the breaking of a wire (wire breaking defect) due to the exfoliation of the barrier metal layer can be avoided. As a result, the semiconductor device of the area pad structure wherein the electrode pad is formed on the active element is constantly mass-produced, whereby the semiconductor device comes to feature lower costs, high quality, and high liability. Besides, since the exfoliation the barrier metal layer is avoided, the yield of the semiconductor device of the area pad structure is surely improved.
It To achieve the above object, another semiconductor device of the present invention is characterized in comprising (1) an active element having a metal wire, the active element being provided on a semiconductor substrate, (2) an interlayer insulating film formed so as to cover the active element, (3) a pad metal for an electrode pad, the pad metal being provided above the interlayer insulating film, and (4) a barrier metal layer provided on the active element with the interlayer insulating film therebetween, so that the pad metal is provided on the barrier metal layer, wherein (i) the interlayer insulating film has at least a level difference compensating film for compensating a level difference of the metal wire, and (ii) only a portion of the level difference compensating film under the pad metal is removed.
According to the foregoing arrangement, in providing the barrier metal layer on the active element on the semiconductor substrate, with the interlayer insulating film provided therebetween, the interlayer insulating film having the level difference compensating film which is mechanically fragile, only a portion under the pad metal is completely removed, from the level difference compensating film which is easily broken by the stress upon bonding. Therefore, the level difference of the metal wire is not compensated, but the breakdown of the level difference compensating film does not occur under the pad metal.
Accordingly, with the above arrangement, the exfoliation of the barrier metal layer from the part thereunder due to the breakdown of the level difference compensating film can be avoided. By doing so, the semiconductor device of the area pad structure wherein the electrode pad is formed on the active element is constantly mass-produced, whereby the semiconductor device comes to feature lower costs, high quality, and high liability. Besides, since the exfoliation the barrier metal layer is avoided, the yield of the semiconductor device of the area pad structure is surely improved. Note that the level difference compensating film may be formed to a minimum thickness necessary for compensating the level difference.
A semiconductor device, having the same arrangement as the aforementioned, may be arranged so as to have a passivation film which is formed so as to cover a large part of the pad metal.
According to the foregoing arrangement, the passivation film which is usually formed so as to partially cover the pad metal is formed so as to largely cover the pad metal. By doing so, in the case where stress is applied to a part under the pad metal due to shock or stress upon bonding or after bonding, thereby causing the barrier metal layer to peel off the part thereunder, the barrier metal layer is held by the passivation film. As a result, exfoliation of the barrier metal layer scarcely occurs. Accordingly, by thus providing the passivation film, possibility of the exfoliation of the barrier metal layer from the part thereunder is surely decreased.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.